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Figure 9.1. RMU Reset Input Sources and Connections.
Reset Managem ent Unit
POR
POWERONn
Cortex-M3
V DD
V DD_REGULATED
BOD
BOD
BROWNOUT_UNREGn
BROWNOUT_REGn
PORESETn
Debug
Interface
RESETn
WDOG
Filter
RCCLR
RMU_RSTCAUSE
Core
SYSRESETn
Peripherals
LOCKUP
Edge-to-pulse
filter
LOCKUPRDIS
SYSREQRST
9.3.1 RMU_RSTCAUSE Register
The RMU_RSTCAUSE register indicates the reason for the last reset. The register should be cleared
after the value has been read at startup. Otherwise the register may indicate multiple causes for the
reset at next startup. The following procedure must be done to clear RMU_RSTCAUSE:
1. Write a 1 to RCCLR in RMU_CMD
2. Write a 1 to bit 0 in EMU_AUXCTRL
3. Write a 0 to bit 0 in EMU_AUXCTRL
RMU_RSTCAUSE should be interpreted according to Table 9.1 (p. 78) . X bits are don't care. Notice
that it is possible to have multiple reset causes. For example, an external reset and a watchdog reset
may happen simultaneously.
Table 9.1. RMU Reset Cause Register Interpretation
Register Value
0bXXX XXX1
0bXXX XX10
0bXX0 0100
0bXXX 1X00
0bXX1 XX00
0bX10 0000
0b1X0 0000
Cause
A Power-on Reset has been performed. X bits are don't care.
A Brown-out has been detected on the unregulated power.
A Brown-out has been detected on the regulated power.
An external reset has been applied.
A watchdog reset has occurred.
A lockup reset has occurred.
A system request reset has occurred.
Note
When exiting EM4 with external reset, both the BODREGRST and BODUNREGRST in
RSTCAUSE might be set (i.e. are invalid)
9.3.2 Power-On Reset (POR)
The POR ensures that the EFM32G does not start up before the supply voltage V DD has reached
the threshold voltage VPORthr (see Device Datasheet Electrical Characteristics for details). Before the
2011-04-12 - d0001_Rev1.10
78
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